1. Field of the Invention
The present invention relates to a semiconductor device, and a wiring-layout design system for automatically designing a wiring-layout for electrode pads provided on a semiconductor device.
2. Description of the Related Art
A representative semiconductor device, which is frequently called an IC (integrated circuit) chip, comprises a semiconductor substrate having a basic multi-layered wiring arrangement provided thereon, and the basic multi-layered wiring arrangement is sectioned into a central internal electronic circuit area section, and a peripheral input/output (I/O) area section surrounding the central internal electronic circuit area section.
In the central internal electronic circuit area section, various active regions are defined in the semiconductor substrate, and patterned wiring layers are formed in the basic multi-layered wiring arrangement, whereby a plurality of internal electronic circuits are produced in the central internal electronic circuit area section.
Also, input/output (I/O) buffers and power supply voltage buffers are produced and arranged in the peripheral I/O area section. The I/O buffers have a smaller size than that of the power supply voltage buffers. The power supply voltage buffers are discretely arranged in the peripheral I/O area section, and the I/O buffers are arrayed between two adjacent power supply voltage buffers, as disclosed in, for example, JP-A-2001-060625.
The internal electronic circuits are suitably and electrically connected to the I/O buffers through the intermediary of conductive paths included in the patterned wiring layers formed in the basic multi-layered wiring arrangement, and each of the power supply voltage buffers is electrically connected to some of the I/O buffers, provided on both sides thereof, through the intermediary of a wiring pattern formed in the basic multi-layered wiring arrangement, to thereby supply the I/O buffers with electrical power.
The semiconductor device further comprises an external multi-layered wiring arrangement provided on the basic multi-layered wiring arrangement, and the external multi-layered wiring arrangement has a plurality of signal electrode pads and a plurality of power supply electrode pads, which are formed on a top surface thereof. Each of the signal electrode pads is electrically connected to a corresponding I/O buffer through the intermediary of a conductive signal path formed in the external multi-layered wiring arrangement, and each of the power supply electrode pads is electrically connected to a corresponding power supply buffer through the intermediary of a conductive power supply path formed in the external multi-layered wiring arrangement.
Each of the conductive power supply paths for establishing the electrical connections between the power supply electrode pads and the power supply voltage buffers has a relatively large width in that a large amount of electric current flows through the conductive power supply path, because all the I/O buffers connected to each of the power supply voltage buffers are supplied with the electric power by the conductive power supply path concerned. On the contrary, each of the conductive signal paths for establishing the electrical connections between the signal electrode pads and the I/O buffers is narrower in comparison with the conductive power supply paths.
In this conventional semiconductor device, the arrangement of the I/O buffers is restricted in that the I/O buffers must be arrayed between the two adjacent power supply voltage buffers. In other words, it is impossible to produce the I/O buffers at a high density in the peripheral I/O area section, and this is disadvantageous in miniaturizing the semiconductor device.
Further, it is troublesome and difficult to automatically design a wiring-layout of the conductive power supply and signal paths in the external multi-layered wiring arrangement, because the wiring-layout must be formed by the wider conductive power supply paths and the narrower conductive signal paths. As a result, a freedom of design of the wiring-layout in the external multi-layered wiring arrangement is considerably restricted.
JP-A-HEI06-061428 discloses a flip-chip type semiconductor device comprising a semiconductor substrate having a basic multi-layered wiring arrangement provided thereon, and the basic multi-layered wiring arrangement is sectioned into a plurality of area sections. In each of the area sections, various active regions are defined in the semiconductor substrate, and patterned wiring layers are formed in the basic multi-layered wiring arrangement, whereby a plurality of internal electronic circuits are produced in the area section concerned. Also, input/output (I/O) buffers are produced in each of the area sections, the internal electronic circuits are suitably and electrically connected to the I/O buffers through the intermediary of conductive paths included in the patterned wiring layers.
The flip-chip type semiconductor device further comprises an external multi-layered wiring arrangement provided on the basic multi-layered wiring arrangement, and the external multi-layered wiring arrangement is sectioned into a plurality of area sections in substantially the same manner as the basic multi-layered wiring arrangement. Each of the area sections has a plurality of signal electrode pads and a pair of power supply electrode pads, which is formed on a top surface of the area section concerned.
Each of the signal electrode pads is electrically connected to a corresponding I/O buffer through the intermediary of a conductive signal path formed in the external multi-layered wiring arrangement. On the other hand, each of the power supply electrode pads is electrically connected to the I/O buffers through the intermediary of a power supply bus formed in the external multi-layered arrangement. In particular, the power supply bus includes a main bus portion connected to the power supply pad concerned, an auxiliary bus portion extending from the main bus portion, and branch portions extending from the auxiliary bus portion and connected to the respective I/O buffers, to thereby supply the I/O buffers with electrical power.
In this conventional flip-chip type semiconductor device, since the I/O buffers are supplied with the electric power through the power supply buses, no power supply voltage buffers are produced in the basic multi-layered wiring arrangement. This is advantageous in miniaturizing the flip-chip type semiconductor device, because the internal electronic circuits and the I/O buffers can be produced at a high density in the basic multi-layered wiring arrangement. Nevertheless, in reality, the miniaturization of the flip-chip type semiconductor device is not hopeful in that the power supply buses occupy a relatively large area in the external multi-layered wiring arrangement. Also, it is troublesome and difficult to automatically design a wiring-layout of the power supply buses in the external multi-layered wiring arrangement, because each of the power supply buses must be formed by relatively complex and widened conductive paths, resulting in restriction of freedom of design of the wiring-layout in the external multi-layered wiring arrangement.